The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, when fabricating field effect transistors (FETs), such as fin-like FETs (FinFETs), device performance can be improved by using a metal gate electrode instead of a polysilicon gate electrode. One process of forming a metal gate structure replaces a dummy polysilicon gate structure with the metal gate structure after other components of the device are fabricated. While this method of forming a metal gate structure has generally been adequate, challenges remain in implementing such fabrication process, especially with respect to improving device performance when feature sizes continue to decrease in FinFETs.